Avionics Full-Duplex Switch Ethernet (AFDX):

 

As the complexity of avionics systems has grown, for both flight-critical items and passenger entertainment, so has the need for increased bandwidth of on-board data buses. The desire for rapid deployment with minimal development and implementation costs, such as wiring, has driven the industry to explore existing off-the-shelf technologies.

 

Avionics Full-Duplex Switched Ethernet (AFDX) is a data network for safety-critical applications that utilizes dedicated bandwidth while providing deterministic Quality of Service ( QoS). AFDX is based on IEEE 802.3 Ethernet technology and utilizes commercial off-the-shelf components. AFDX is a specific implementation of ARINC Specification 664 Part 7, a profiled version of an IEEE 802.3 network per parts 1 & 2, which defines how Commercial Off-the-Shelf networking components will be used for future generation Aircraft Data Network (ADN). The six primary aspects of AFDX include full duplex, redundancy, deterministic, high speed performance, switched and profiled network.

 

Overview of AFDX

 

AFDX adopted concepts (token bucket) from the telecom standard, to fix the shortcomings of IEEE 802.3 Ethernet. By adding key elements from Pseudo Wire over Ethernet (PWE) to those already found in Ethernet , and constraining the specification of various options, a highly reliable Full-Duplex deterministic network is created providing guaranteed bandwidth and Quality of Service. Through the use of Full-Duplex Ethernet, the possibility of transmission collisions is eliminated. However, though bandwidth and maximum end-to-end latency and jitter, links are guaranteed, there is no guarantee of packet deliver. A highly intelligent switch, common to the AFDX network, is able to buffer transmission and reception packets. Through the use of twisted pair or fiber optic cables, Full-Duplex Ethernet uses two separate pairs or strands for transmit and receiving data. AFDX extends standard Ethernet to provide high data integrity and deterministic timing. Further a redundant pair of networks is used to improve the system integrity

 

The main elements of an AFDX network are:

 

• AFDX End Systems

• AFDX Switches

• AFDX Links

 

Virtual Links

 

The central feature of an AFDX network are its Virtual Links (VL). In one abstraction, it is possible to visualise the VLs as an ARINC 429 style network each with one source and one or more destinations. Virtual Links are unidirectional logic path from the source end-system to all of the destination end-systems. Unlike that of a traditional Ethernet switch which switches frames based on the Ethernet destination or MAC address, AFDX routes packets using a Virtual Link ID. The Virtual Link ID is a 16-bit Unsigned integer value that follows the constant 32-bit field. The switches are designed to route an incoming frame from one, and only one, End System to a predetermined set of End Systems. There can be one or more receiving End Systems connected within each Virtual Link. Each Virtual Link is allocated dedicated bandwidth [sum of all VL Bandwidth Allocation Gap (BAG)rates x MTU] with the total amount of bandwidth defined by the system integrator. However total bandwidth cannot exceed the maximum available bandwidth on the network. Bi directional communications must therefore require the specification of a complimentary VL. Each VL is frozen in specification to ensure that the network has a designed maximum traffic, hence determinism. Also the switch, having a VL configuration table loaded, can reject any erroneous data transmission that may otherwise swamp other branches of the network. Additionally, there can be sub-virtual links (sub-VLs) that are designed to carry less critical data. Sub-virtual links are assigned to a particular Virtual Link. Data is read in a round robin sequence among the Virtual Links with data to transmit. Also sub-virtual links do not provide guaranteed bandwidth or latency due to the buffering, but AFDX specifies that latency is measured from the traffic regulator function anyway.

 

The Ethernity ENET uses its fragmentation inherent feature to enable transmission of shorter packets that results in reduce overall latency and jitter and with the use of it hierarchical queuing and hierarchical shaping it supports the VL scheduling requirements

 

BAG Rate

 

BAG stands for Bandwidth Allocation Gap, this is one of the main features of the AFDX protocol. This is the maximum rate data can be sent, and it is guaranteed to be sent at that interval. When setting the BAG rate for each VL, care must be taken so there will be enough bandwidth for other VL's and the total speed cannot exceed 100Mbit/s. With minor adaptation to the Metro Ethernet compliance policer available on the ENET, the ENET AFDX product now support the BAG rate feature

 

Switching of Virtual Links

 

Each switch has filtering, policing, and forwarding functions that should be able to process at least 4096 VLs. Therefore, in a network with multiple switches (cascaded star topology), the total number of Virtual Links is nearly limitless. There is no specified limit to the number of Virtual Links that can be handled by each End System, although this will be determined by the BAG rates and max frame size specified for each VL versus the Ethernet data rate. However, the number sub-VLs that may be created in a single Virtual Link is limited to four. The switch must also be non-blocking at the data rates that are specified by the system integrator, and in practise this may mean that the switch shall have a switching capacity that is the sum of all of its physical ports.

 

Jitter

 

The End System (ES) may introduce jitter when transmitting frames for a given VL. This jitter is defined as the interval from the beginning of the BAG to the first sent bit of the frame being transmitted at the VL's maximum allocated bandwidth . This jitter may be introduced by the transmitting technology and the traffic-shaping function. A given ES may have to transmit data for multiple VLs, so a frame from one VL can be delayed up to the maximum allowed jitter value to limit the instantaneous ES frame rate and thus accommodate frames from other VLs.

 

By the use of the ENET Jitter buffer user may be able to gain end to end jitter control on the entire ADN.

 

Latency

 

Although ARINC 664 Part 7 does not specify a maximum system latency, any supplier is required to specify the upper limit of latency for any system delivered. The specification does set down limits for some aspects of system latency. to reduce latency the ENET can employ its Fragmentation option that reduces latency between packet in scheduling scenario.

 

Frame Format

 

The destination and source addresses listed contain the MAC addresses for the End Systems. Actual IP address information is contained in the IP Structure block. The UDP structure identifies the appropriate application port. The AFDX payload ranges from 1 to 1471 bytes.Payload sizes less than 17 bytes must be padded to maintain a minimum length of 17 bytes.

 

Redundancy

 

An AFDX network is constructed so there are two independent paths (including MACs, PHYs, and cabling) between each ES, as well as redundant switches to protect the network from a failure at the MAC level or below. The default mode is to transmit the same frame (with identical frame sequence numbers) across both networks. The receiving ES then accepts the first valid frame and passes it to the application. Once a valid frame is received, any other frame with the same sequence number is discarded. The redundancy option must be configurable—frames for a given VL may be sent along either or both of the networks.

 

Optimize FPGA AFDX End System and Switch System on a Chip ( SoC)

 

Since AFDX utilizes the Ethernet protocol at the MAC layer, it is possible to use high performance COTS switches with Layer 2 routing as AFDX switches for testing purposes as a cost-cutting measure. However some features of a real AFDX switch may be missing including traffic policing (BAG), AFDX redundancy functions, Frame Format and optimized lateacy and jitter.

 

To support the above added technology and feature above the pure Ethernet solution, Ethernity have adapted it ENET Fabric Flow Processor to support the AFDX variant, and is now ready for ADFX implementation.

By using FPGA based solution customer can easily perform all the Avionic approvals, by examining the FPGA code, and with the various options of FPGAs for industrial, Aerospace or military solution customer can choose the right FPGA for his application.