Carrier Ethernet Switch reference design based on ENET48xx Carrier Ethernet Switch SoC on FPGA to support 40G swtiching capacity based on Xilinx's Kintex 7 FPGA
20 GbE i/f interfaces or 18 GbE and 2 x 10GE interfaces
10 x RJ 45 copper, 8 SFP and two SFP+
Option for final product with box and power supply
On-board DDR3 operates at 800MHz for packet memory, search and paramaters
Motorola MPC8306, Power QUICC-IIICPU environment for control and managment
RS232 and GbE portfor Out-of-band management
Supported documents
API/CLI Document
Evaluation board schematics
Application note
Board Manual
ATP
Overview:
Ethernity Networks ENET48xxRD is the Reference design kit for the ENET48xx 40Gbps Carrier Ethernet Switch SoC on FPGA. It supports up to 18GbE ports and 2 10GE SFP+ . The Development Kit minimizes development time by facilitating evaluation, testing, and design of Carrier Ethernet Switch built on the ENET48xx Packet Flow processor and Traffic Manager device therefore minimizing time-to market for our customers.
Block Diagram:
Hardware Elements
Entire Carrier Ethernet Switch, and traffic manager integrated on 28 nm Kintex 7 FPGA
20GbEs user ports ( 10 fiber, 10 copper)
2 x 10GE SFP+ interfaces
On-board DDR3 for packet memory, search and parameters entries
Motorola MPC8306, Power QUICC-III environmentA single low cost FPGA
32MB (option up to 128MB) SDRAM on the 32-Bit Address and Data bus.
32MB Code Flash and 1MB Boot Flash
RS232 and FE ports for Out-of-band management
Software support
OS independent
Linux and Vx works operating system support
LSP – Linux Support PackageSoftware download via ftp
Efficient Boot Loader provides flexible and fast software updates
CLI – Command Line Interface accessible via Serial Port and remote Telnet client
Full API support
Option for 3rd party metro switch software application
Reference Design Package
Ethernity's ENET48xx is built for easy evaluation and product development with the ENET48xx device. The reference design includes all necessary documentation and collateral information to accelerate product development and minimize time-to-market.