Description:

 

The ENET3875/G.999 Access Flow Processor is a Virtual ASSP SoC on FPGA serving High thgouhput DSL line card  . 

 

The ENET3875/G.999 is a Multi Service Fabric Flow Processors (FFP) integrating packet processing, protocol interworking, traffic management, G.999.1 ch Ethernet and  Layer 2/3/4 switch, and can come with higher end version under ENET4200 to support 2 10GE ports and 16 G.999.1 serving 256 DSL modem on single chip, lower end version with ENET3825 with single GbE to the the network and single G.999.1 i/f towards the modems supporting 16 modems. 

 

The ENET38xx design is based on an extremely efficient architecture resulting in 80% die size reduction,  enabling an extremely cost effective implementation based on low cost FPGAs. The Ethernity ENET38xx solution retains the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASIC solutions. ENET38xx is based on atomic engines pipeline architecture, and supports performance of up to 8Gbps on ultra low cost FPGA, with software configurable L2 to L4 protocol interworking, hierarchical multi field classification and flow Identification, Virtual Ethernet Switch used for VPLS, E-LAN , E-TREE and E-Line, Hierarchical policing, performance monitoring, packet editing, Hierarchical scheduling and shaping .

 

The ENET3875 protocol interworking includes software support for packet editing, which provide the ability to receive packets in any format and change the protocol per virtual output port to any other protocol, hence it supports Ethernet II, SNAP, Q-in-Q,  PPP, PPPoE , PPPoA ,HDLC, L2TP, and AAL5.

 

Detailed Features:

 

Classification

 

• Identifies flow and assign several flow IDs per stream, based on 36 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the first 128 bytes of each frame

• Assigns packet priority based on Ingress priority mapping configuration.

• Up to 32K flows filter for any classified packet based on the set of rules and set of the 64 configurable fields

 

Switching and Routing

 

• Fully IEEE 802.1Q compliant Ethernet switch with up to 128K Ethernet MACs, and 16K Active Network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS or other packet fields programmed by the software and up to 4K Multicast groups.

• Configuration forwarding/switching decision per flow including connection oriented , L2, L3 or L4 forwarding decision

• 32 software programmable / configurable search tables

• Configurable forwarding key and learning key per flow

• Force association of specific MAC to a certain logical port and service.

• 16K L3 address for supporting L3 forwarding

• Partitioning of MAC address per VPNL2

• Control packets classifier for both user and Network L2 control protocol packets

• Flexible forward decision per port per protocol with the ability to forward transparently, to CPU or Discard

• Support include ARP, DHCP, IGMPv2, IGMPv3 and other based on flexible configuration options

 

Quality of Service (QoS)

 

• Eight priority queues per  virtual port ( virtual modem port) 

• Priority Assignment per Port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS

• Configurable L3/L2 Priority profiles per portIngress and Egress priority mapping per flow

 

Policing and Shaping

 

• Extended Metering according to Three Color scheme as defined by MEF 10 including color aware and coupling flag modes configured per flow

• Supports up to 2K flows

• Each ingress and egress flow can be configured in a granularity of 64Kbps up to 100Mbps

 

Traffic Management

 

• Support of Jumbo frames up to 9.6KB

• Supports eight priority queues per port / virtual port

• Hierarchical scheduling

• Programmable values for drop level.

• Two Weighted Fair Queuing hierarchies

• TCP Friendly Algorithm implemented

 

Packet Editing

 

• Extract, append, or swap in the egress any type of Layer 2/3/4 headers programmed by software, including, Q-In-Q,  PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP,L3,  or any other header up to 128 bytes, controlled and configured by software.

• L2 and L3 loop backs including swap of MAC SA and DA, Swap of IP.

• Stamp data at the bit/byte level anywhere within the first 128 bytes including priority remapping, bytes count, sequence ID and DSCP.

 

Traffic Monitoring

 

• L2/L3/L4 Control packets classifier for both user and Network L2 control protocol packets per flow

• Flexible forward decision per port/flow per Protocol with the ability to forward transparently, to CPU or Discard

• OAM packets classifier for both user and Network including support for 802.1ag

• Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or Discard

• Integrate packet generator and analyzer to support generation and analyzing of OAM packets and full support for Y.1731

 

IGMP Proxy

 

• IGMP V2 and V3 compliance

• IGMP packet snooping to processor in the U/S direction

• Forwarding and multicast classification based on Source IP and Destination IP

 

EFM bonding & Fragmentation

 

• Supports 6 to 16 G.999.1 Channelized Ethernet ports

• Supports 8  EFM Bonding groups according to 802.1ah

 

DDR SDRAM Interface

 

• External 16-bit DDR2-SDRAM 400 MHz interface

• Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components

 

Host CPU Interface

•  OptionMotorola PowerPC 1&2 Glueless interface

• Up to 66Mhz with 8/16/32 bit bus width

• MII interface

 

 Interfaces 

 

ENET3875/G.999

 

• 2 x 2.5G SGMII

• 6 x G.999.1 GbE i/f supporting 48 VDSL ports

• MII

• CPU

 

ENET4200/G.999

 

• 2 x 10GE XFI

• 16 x G.999.1 GbE i/f supporting 256 VDSL modems

• GMII

• CPU

 

ENET3825/G.999

 

• 1 x 2.5G SGMII

• 1 x G.999.1 GbE i/f supporting 16 g. fast ports

 

Reference Design Kit