Description:

 

The ENET38xx Access Flow Processor is a family of high performance configurable flow processor and traffic manager solutions optimized for the Metro Access Market. ENET38xx is specially focuses on the Carrier Ethernet Access , Metro Ethernet Demarcation, IP DSLAMs, ONU for MDU market in the form of throughput, functionality and conformance to standard requirements.

 

The ENET38xx is a Multi Service Fabric Flow Processors (FFP) integrating packet processing, protocol interworking, traffic management,  Layer 2/3/4 switch.

 

Ethernity’s ENET38xx Multi Service Fabric Access Processor family is optimized for the Mobile Backhaul transmission network and Carrier Ethernet Metro markets. Compliant with Metro Ethernet Forum specifications and IETF PWE3, The ENET38xx is uniquely positioned to deliver an optimal solution for, Pseudo Wire Gateways, TDM and Ethernet Access Devices (EAD), Carrier Ethernet Microwave, Cellular Base Stations and Broadband Access DSL Cards including support for integrated EFM Bonding.

 

The ENET38xx design is based on an extremely efficient architecture resulting in 80% die size reduction,  enabling an extremely cost effective implementation based on low cost FPGAs. The Ethernity ENET38xx solution retains the flexibility and programmability of FPGAs, while providing a solution that is cost and power competitive with ASIC solutions. ENET38xx is based on a atomic engines pipeline architecture, and supports performance of up to 8Gbps on ultra low cost FPGA, with software configurable L2 to L4 protocol interworking, hierarchical multi field classification and flow Identification, Virtual Ethernet Switch used for VPLS, E-LAN , E-TREE and E-Line, Hierarchical policing, performance monitoring, packet editing, Hierarchical scheduling and shaping .

 

The ENET38xx protocol interworking includes software support for packet editing, which provide the ability to receive packets in any format and change the protocol per virtual output port to any other protocol, hence it supports Ethernet II, SNAP, Q-in-Q, MAC-in-MAC, MPLS-TP, PPP, PPPoE , PPPoA ,HDLC, L2TP, AAL5 or any type of L2 protocol.

 

Detailed Features:

 

Classification

 

• Identifies flow and assign several flow IDs per stream, based on 36 flexible /programmable fields including TCP, UDP, IP address, MAC, port number, L2 header, LSP, or based on information available in the first 128 bytes of each frame

• Assigns packet priority based on Ingress priority mapping configuration.

• Up to 32K flows filter for any classified packet based on the set of rules and set of the 64 configurable fields

 

Switching and Routing

 

• Fully IEEE 802.1Q compliant Ethernet switch with up to 128K Ethernet MACs, and 16K Active Network TAGs/streams comprising from VLANs, AAL5, QTAG, MPLS, or other packet fields programmed by the software and up to 4K Multicast groups.

• Configuration forwarding/switching decision per flow including connection oriented (PBT), PBB, L2, L3 or L4 forwarding decision

• Full compliance with PBB-TE / PBT and PBB

• Switching based on inner MAC and combination of Network Tags

• Switching based on outer MAC and combination of Network Tags

• 32 software programmable / configurable search tables

• Configurable forwarding key and learning key per flow

• Force association of specific MAC to a certain logical port and service.

• 16K L3 address for supporting L3 forwarding

• Partitioning of MAC address per VPNL2

• Control packets classifier for both user and Network L2 control protocol packets

• Flexible forward decision per port per protocol with the ability to forward transparently, to CPU or Discard

• Support include ARP, DHCP, IGMPv2, IGMPv3 and other based on flexible configuration options

 

Quality of Service (QoS)

 

• Eight priority queues per virtual port

• Priority Assignment per Port, 802.1p tag, MPLS (LLSP or ELSP), L3 DiffServe Code Point (DSCP) or TOS

• Configurable L3/L2 Priority profiles per portIngress and Egress priority mapping per flow

 

Policing and Shaping

 

• Extended Metering according to Three Color scheme as defined by MEF 10 including color aware and coupling flag modes configured per flow

• Supports up to 4K flows

• Each ingress and egress flow can be configured in a granularity of 64Kbps up to 100Mbps

 

Traffic Management

 

• Support of Jumbo frames up to 9.6KB

• Supports eight priority queues per port / logical port

• Hierarchical scheduling

• Programmable values for drop level.

• Two Weighted Fair Queuing hierarchies

• TCP Friendly Algorithm implemented

 

Packet Editing

 

• Extract, append, or swap in the egress any type of Layer 2/3/4 headers programmed by software, including MAC-in-MAC, Q-In-Q, MPLS, PPPoE, PPPoA, ATM to Ethernet (AAL5), PPP, HDLC, L2TP,L3,  or any other header up to 128 bytes, controlled and configured by software.

• L2 and L3 loop backs including swap of MAC SA and DA, Swap of IP.

• NAT/NAPT

• Stamp data at the bit/byte level anywhere within the first 128 bytes including priority remapping, bytes count, sequence ID and DSCP.

 

Traffic Monitoring

 

• L2/L3/L4 Control packets classifier for both user and Network L2 control protocol packets per flow

• Flexible forward decision per port/flow per Protocol with the ability to forward transparently, to CPU or Discard

• OAM packets classifier for both user and Network including support for 802.1ag

• Flexible forward decision per port per OAM type with the ability to forward transparently, to CPU or Discard

• Integrate packet generator and analyzer to support generation and analyzing of OAM packets and full support for Y.1731

 

IGMP Proxy

 

• IGMP V2 and V3 compliance

• IGMP packet snooping to processor in the U/S direction

• Forwarding and multicast classification based on Source IP and Destination IP

 

Fragmentation

 

• Supports Channelized Ethernet according to G.999.1

• Supports EFM Bonding according to 802.1ah

 

Pseudo Wire

 

• Full Support for: SAToP and CESoPSN

• Adaptive Clock Recovery (1588v2), Common Clock, External Clock and Loopback Timing Modes

• Jitter and wander of recovered clocks conform to G.823/G.824, G.8261,Jitter buffer – programmable up to 128 msec

• Option for E3/DS3

• ATMoPW

 

Synchronization over Packet

 

• 1588 End to End Transparent Clock1588v2

• Slave mode clock recovery through third part software

• Synchronous Ethernet

 

DDR SDRAM Interface

 

• External 16-bit DDR2-SDRAM 400 MHz interface

• Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components

 

Host CPU Interface

•  OptionMotorola PowerPC 1&2 Glueless interface

• Up to 66Mhz with 8/16/32 bit bus width

• MII interface

 

Configurable Interfaces options

• 8 x SGMII together with 4 x RGMII

• 4 x 2.5G SGMII

• 6 x G.999.1 GbE i/f supporting 48 VDSL ports

• 4 x Utopia/POS II supporting up to 96 ports with dual latency

• 40 SSSMII

• SPI-3

• 32 x E1/T1s - PCM

• 4/8 x Ch OC-3/STM-1 - SBI

• Other per customer request

 

Ordering Options

 

ENET3XXX-YYYYYYYY-Z-(N)

 

where,

 

XXX Throughput required, see details bellow.

YYYYYYYY Interfaces, see Example.

Z C for commercial, I for Industrial

N N for Lead-Free, Blank for Leaded

 

XXX      Throughput

825      up to 2.5 Gbps

850      up to 5 Gbps

875      up to 7.5 Gbps

 

Interface and application options

 

Y1: num of RGMII Ethernet ports

Y2: num of ATM or POS Or SPI or SBI ports ( Number of OC-3/STM-1 on SBI)

Y3: NONE(0) or BONDING(B) or ATM(1) or POS(2) or SPI-3(3) or SBI (4)

Y4: num of Octal S-SSMII Ethernet ports

Y5: num of octal E1\T1 ports

 

Transceivers:

 

Y6: num of 1 GbE transceivers (Note: A for 10, B for 20, C for 12 and D for 24)

Y7: num of 2.5 Gbps transceivers

Y8: num of XAUI transceivers

 

Reference Design Kit