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ENET 3825PW / ENET3700PW

 

Features

 

  • Combined Switch and Pseudo Wire on Xilinx's Spartan 6 FPGA

  • Flexible interface support that can be customized to any port / interface configuration·

  • Universal gateway solution for legacy protocols

  • Sync Ethernet support

  • SAToP and CESoPSN with support for up to 336 PW channels

  • Hardware Fast protecting switching within micro seconds

  • 1:1, N:1 and Peer to Peer network architecture 

  • Clock Recovery can be supported using third party IEEE 1588v2 clock recovery software application mapped to Ethernity Hardware, or external Clock recovery

  • Jitter Buffer granularity of 125 micro sec ( TDM frame)

  • Programmable Packet Editor supporting per flow multiple actions of Append/ Swap/ Extract/ stamp in any preconfigured location in the first 128 bytes

  • Management is performed through , generic CPU interface, MII, GMII or integrated CPU

Description:

 

Ethernity’s ENET38xxx Multi Service Fabric Access Processor family is optimized for the Mobile Backhaul transmission network and Carrier Ethernet Metro markets. Compliant with Metro Ethernet Forum specifications and IETF PWE3 RFC the ENET3800PW is uniquely positioned to deliver anoptimal solution for, Pseudo Wire Gateways, Carrier Ethernet Microwave and Wireless Base Stations.

 

The ENET3700PW-S is a pure Channelized SAToP implementation to support 4xSTM-1/OC-3 solution integrated onto Spartan 6 150 FPGA with up to 336 PWE channels.

 

The ENET3820PW-E is a pure SAToP implementation to support up to 64 E1/T1s integrated intoSpartan 6 75 FPGA with up to 64 PWE channels.

 

The ENET3xxx's IP is based on an extremely efficient architecture resulting in 80% die size reduction,and can be integrated into low cost FPGA, in a different interface configuration and internal memoryenabling an extremely cost effective implementation based on low cost FPGAs, that retains the flexibilityand programmability of FPGAs, while providing a solution that is cost and power competitive with ASICsolutions.

 

Detailed Features:

 

Classification

 

  • Packet classification based on first 128 bytes in packet

  • Configurable functional actions: filtering, trapping, mirroring, Packet editing (create/modify/delete), QoS remarking

  • Control filtering and forwarding

​

Pseudo Wire

 

  • Full Support for: SAToP and CESoPSN supporting up to 336 channels

  • Adaptive Clock Recovery (1588v2), Common Clock, External Clock and Loopback Timing Modes

  • Supporting all PWE encapsulation options SAToP control word with and without RTP, including

    • 2xMPLS tags with/without VLAN

    • VLAN + 1 MPLS tag

    • MPLS over IP with/without VLAN

    • MPLS over UDP over IP with/without VLAN

​

  • Jitter and wander of recovered clocks conform to G.823/G.824, G.8261,

  • Configurable Jitter buffer size up to 256 msec

  • Jitter buffer granularity of 125 micro second

  • Configurable PW frame size

  • Option for E3/DS3

  • ATMoPW

 

Synchronization over Packet

 

  • 1588 End to End Transparent Clock1588v2

  • Slave mode clock recovery through third part software

  • Synchronous Ethernet

 

DDR SDRAM Interface

 

  • External 16-bit DDR2-SDRAM 400 MHz interface

  • Supports 128/256/512Mbit 16 bit width standard PC DDR2 SDRAM components

 

Host CPU Interface

 

  • OptionMotorola PowerPC 1&2 Glueless interface

  • Up to 66Mhz with 8/16/32 bit bus width

  • MII interface

 

 Interfaces options

 

ENET3700PW

 

  • 4 x STM-1/OC-3 through SBI interface (336ch)

  • 2 x 100/1000 SGMII interfacesï‚·

  • 1 x DDR2s for packet bufferï‚·

  • 1 x MII for CPU

​

ENET3825PW

 

  • 64 E1/T1, DS3, 16 E1/T1, or 8 E1/T1s through PCM interface

  • 2 x 100/1000 MII interfacesï‚·

  • 1 x DDR2s for packet bufferï‚·

  • 1 x MII for CPU

 

 

Reference Design Kit

 

 

 

Product Briefs

 

 

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